Multiply Clocked Properties and Sequences and Operators 'and', 'or', etc

SystemVerilog Assertions and Functional Coverage From Scratch Multiply Clocked Properties and Sequences
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Hello, and welcome to lecture number 16 on multiple clouds. As you know, there are hardly any designs today which work off of a single clock. I can think of any SOC today, which can have only one clock domain throughout the chip. What that means is when you have multiple clock domains, you will go from one clock domain to the other, and your assertion will require that you will have some property or some expression passing on one clock. But then you need to check for another expression meaning you're going from one block to the other block. The other expression needs to match on some different clock.

So, let's take step by step approach and see how multiple clocks are supported by SBA. Okay, I'll start with an example and then move back and forth between theory and Example. So let's look at this sequence sequence m clocks. It says that at pauses of clock zero, a should be true. And lb lb one at pauses of clock one, B should be true. Now that looks very benign and simple.

The first reaction you may have is that okay, there is a pom pom one clock delay, which means that after pauses of clock zero when A is true, one clock later on pauses of clock one B should be true. That is not correct. This spawn found one does not necessarily mean a delay of one clock. It basically depends on whether the clocks clock zero and clock one are in phase or out of phase. And I will show you an example of each of those. So, off the bat think of bond bond one as a concatenating.

Concatenating is not an operator but concatenating delay between singly clocked sub sequences. And hence according to LRM multiply the clock sequences are built by concatenating single clock sub sequences using the delay concatenation found found one or Hong Kong zero and then I will show you that you can only use one or zero for clock delay and nothing else. So, again, here, one clock delay does not necessarily mean an entire clock. Okay, so let's look at this timing diagram. So advantage of clock zero a needs to be true and here's your knowledge of clock zero. And a is indeed true.

So let's see when B arrives and the relationship between clock zero and clock one. So purposely, I have put clock one to be out of phase with clock zero. So, now look at this very carefully at pauses of clock zero is true and we are saying that one clock later we should be true, but it does not mean one clock what it really means is after this pauses of clock zero, which is the nearest strictly subsequent pauses of clock one, if you look at it, this is pauses clock zero then the very next pauses clock one is here. Then, this property this sequence sorting means that at bondage of drop one meaning these piles of drop on Venus will be true. Just to repeat you know we are not waiting for an entire clock zero or we are not waiting for an entire clock. One.

We are not waiting up to either here or here. We are simply looking For the very next positive clock one very next, right Africa's zero and that's when we supposed to be true. And that's what there's one clock delay upon point one means when when it concatenates two sub sequences, each one working in in its own clock domain. So this is about the most important thing you need to understand if you don't understand how the how the clock domains cross and how the inferences are taking place, then you will not understand the results of your sequence passing or failing. So, another way to remember is that on match of a apologies of drug zero, BonBon one moves the time to the nearest strictly subsequent positive clock one, and the sequence ends at that point with a measure of V as I just said, explain to you in this timing diagram.

So let's look further. This slide is simply to show that in the previous slide, I had zero in clock one out of phase. And here I'm giving both of them in phase. So now now if you look at positive 08 is true, which is a next very subsequent pauses of clock one. It's not here, it's here. And so this is where we need to be true.

The point I'm trying to make is that when they are in phase, they're basically identical clocks. And when they are identical clocks, if you look at the sequence, clocks, zero is true one clock later at clock pauses of clock one B needs to be true. You can rewrite this C simply since clock zero and clock one are identical at policy. clock zero is true. And one clock later at pauses of clock zero, again, B is true. Or you can further simplify this by simply saying that at positive clock zero, a 111 b, this is what you have seen throughout the course, up until now.

So the only point I'm making here is that if they're out of phase, for example, and they can be out of phase in phase or with totally different duty cycles, or even staggered, as opposed to out of phase only, and all you care for is that after the policies of clock zero in this particular sequence, you look for the very next positive clock one, which ends up half a clock later here, and which ends up one full clock later here, from here to here. So let's look at before we move further, like I just said in an earlier slide, that The concatenating delay between the two sub sequences is either lb lb one or lb lb zero. So, for example, if you end up saying that at pauses of clock zero is true and two clocks later lb lb to a positive clock one B is true this is not allowed because one for two is obviously not one or zero.

Similarly, now this is okay even though there's bom bom, bom bom do as the concatenating delay between the two sub sequences and that's because the clock on both sides both sub sequences is the same, which makes sense then there is no problem you can use anything like we have seen so far in the in the class, you can have any kind of delay or operator in the middle and this is to show that Monday clock sequences you cannot you cannot intersect them, you cannot end them you cannot order them you cannot, not them. I want to make sure that these rules apply only to sequences and not to properties and hence I put sequences in italics here. These illegal and legal scenarios are only applicable to sequences. So again to reiterate, follow sequence the only operator allowed between two sub sequences with different clocks is either lb lb one or pom poms zero, anything else will give you either a compile or a most likely a compile error.

So, now let's look at the multiplay clock properties. And the first thing I want to point out is that as far as the clock resolution is concerned, what I just explained to you with in phase and out of phase claws apply Hear as well. So I just take it one step further. Now since this is a property, and all the properties have implication operator, they don't have to have, but properties is where you connect antecedent with the consequent. So let's say you have pauses clause zero, a being true. It implies that if d ad pauses cross zero, we know that with the this is the overlapping implication.

And the clocks are the same on both sides. So it's basically equivalent to this clause at paws edge of proc zero, a implies you don't need to have this clock anymore if d be so here the clock this clock is resolved, quote unquote, with the the clock that appears before a because they are the same clock. Now let's look at this example. Again, the talks are the same both in the antecedent side and the consequent side. And if you look at carefully, these clocking here, again, let me repeat does not necessarily mean that for example, let's say you wait for pauses of zero as true, then you don't wait for the next pauses of claw zero for B to be true. This does not mean the next pauses of clock and this also does not mean next, pauses of clock.

What this entire thing means is that these clocks are resolved with the passage of clock zero here and there. So this particular property is equivalent to at pauses of clock zero, a implies or lapping, if d ELLs deliberate. So there are not three clocks moving along there. It's just one clock because of The three clocks are the same. Now let's take an example where the clocks are different. As a matter of fact same as well as different on two sides.

This property says that at pauses of clock zero, a being true. If it's true, it implies that if be at pauses of clock zero same clock be through one clock later at pauses o clock one which is a different clock z is true. So, if d either you do something at the same clock and wait for one clock and then at a different clock, you go and look for z to be true else again with the same clock. You wait for tilde to be. So, just like I explained in the previous two examples, this is equivalent to at posits clock zero a implies overlapping implication. If b this is resolved with the previous one, if d Be, but this is a different route.

So, you have to it has to preserve that clock one clock later at passage of clock one z is true and then again the clock zero is the same as the antecedent clock. So, l Stiller B. So, once you see and I will show you even further rules governing how clocks are quote unquote resolved for multiple clock properties and this is illegal. Why, because what we are doing here is you have pauses of clock zero. Again you have pauses of clock zero on the consequence side, but then you also have a different clock called clock one. You cannot have an overlapping operator when you go from one clock domain To another clock away, but this particular condition is odd this particular restriction is maybe being removed from 2009 and 2012 LRM if you are using only 2005 then this will be illegal.

But in 2009 and 12 LRM you can have different clocks between the antecedent and consequent even with an overlapping operator in the middle. So, let me now show you interesting way of ending or whoring multiplay clock properties, not sequences sequences do not allow and or not operator. So, I'll just take one operator and for example, what I'm seeing in this property is that a certain property at particular Zero. If it's true, then one clock letter M clocks should hold. And m clocks says that it pauses of clock one, B is true. And this is the end operator and it pauses o clock to see through.

So I have basically taken three different clocks now, and there is an end of two clocks. So let's see how this is going to work. Let's start with that positive clock zero is true, which is this particular condition. Now, we are saying that at after this one clock later, all this is a pompom one again is a concatenation operator here at pauses of clock one we should be true. So just like I explained before, what this What that means is after pauses of clock zero, which is a next subsequent posit of clock, one which is this one. So at that point, we need to be true.

And now that is an AND operator, so this is the bondage of crock on Venus to be true, as well as pauses of clock to see needs to be true. Together, it's an ad. So, C is on Glock two. What that means is that the various subsequent pauses are brought to after pauses of clock zero. So, positive clock zero is here, and the very next positive block two is here, that this edge seems to be true. If this relationship is maintained, then the property will pass else it will fail.

So again, the the key is that you need to have a unit to understand what the very next subsequent clock age or different clock means in relation ship with the first one. So BNC must be true at immediate subsequent, any word you want to use next pauses of block one and block two respectively after the pauses of clock zero this this example is pretty much the same but what I've done here is I've taken for example here we had in M clocks clock one and drop two. I have purposely made Botox will be the same. But then this Glock one is different from TruXedo. So everything else is identical to the previous slide the properties the same, only that I want to show how and and between two identical clock works. So again, as Ron Paul There's no cross zero.

So be nice to be true on the very next subsequent pauses of block one. So b is true, but since there is an end and the clock is the same, even c needs to be true at the same positive clock one. So just just to give you a different flavor of how and would work in multiple clock properties Okay, let's go back to the multiply clock properties clock resolution, because you will be writing very complex properties you will have three four clock domains all tied together, and you will be jumping from one clock to the other checking for expressions. And you need to know which clock will be applied to reach expression or reach subsequence. So let's take this example. Positive cross zero a bomb fun one B bomb phone one at positive crock, one c implies the hottest club going to migrate quote unquote.

Let's look at it. So a will get the clock will get the positive crossover it's it's obvious it's right here, then this clock moves forward and there is no other clock in front of B so pauses of clock zero also applies to B, but then the clock changes. So C will obviously get pauses of clock one. But note that after this, this clock pauses of clock one does not move forward to D rather, bothers grace zero will be applied to D. So D will be quote unquote evaluated sampled on pauses of crops. Zero not pauses or clock one this is how progress solution takes place on the other side of the antecedent, this clock propagates so called zero flows through a then in the parenthesis to be. See now, why does the get towards zero and not talk one note that this entire subsequence is in parenthesis.

And what they LRM says is that the scope of a clocking event flows into parentheses parenthesize sub expression meaning here and if the sub expression is a sequence also flows left to right across a parenthesize that means, from here from this B to this C that we can understand. However, the scope of the clocking event does not flow out of enclosing parenthesis The scope of a talking event. So here's the blocking event inside the parenthesis, it does not flow outside the parentheses. And because of that reason why D gets pauses across zero and not pauses of clock one. Let's look at an example. Let's say you have sequence s, I'll go bottom top, and it says that pauses of clock A, this will be true.

BonBon one s one subsequence needs to be true later as to subsequence need to be true. And then finally F. Another signal needs to be true. Now, this a will get pauses of clock because it's right there. Now let's look at s one. You go to S one you have pauses of clock zero. So We will get pauses across zero because it's right there.

And one clock quote unquote one clock later See also will get pauses of clock zero, because it's part of the same sequence. Similarly, one clock later, again one clock does not necessarily mean one clock, but the very next subsequent edge of pauses of clock one in this case. So, Esther will do will work off of pauses clock one, he will also work off of pauses of clock one because they are all part of the same sequence. But once you come out of as two qualities of grok one will not be applied to F, rather pauses of clock will be applied to f. So, you need to be very careful when you write multiple clock properties on how grok is resolved, or what I call how the clock flows, how it flows from one subject sequence to the other set subsequence one expression to the other because if you don't understand this concept clearly then your multiplay clock properties will be incorrect or you may spend too much time debugging so let's look at the just like for sequences what is legal and illegal for properties as I just said you know sequences cannot use and or not etc.

But while they play clock properties can be formed using and or not. And we just saw the example of an end here, Grace zero on the antecedent side clock one on the consequent side and that is a non overlock labbing operator. So this is a perfectly legit property. Now, here like I just say And then earlier slide, the clocks are different, but the implication operator is overlapping. Now this used to be illegal in 2005. But in 2009 and 2012, it is legal.

What that means is let's say as soon as as true at the same clock, if pauses of clock one is also true, you will evaluate me. In 2005 LRM, the clock had to advance just like a non overlapping before we looked at be not so true in 2009 and 2012. So, please make a note of it, it depends on which simulator you're using. If that simulator does not support 2009 then it will give an error if it supports then it will not give you an error. Again, this is perfectly fine overlapping even though there are two different types The two clauses are the same. So basically this property resolves in the passage of clause zero, a implies B, we kind of saw something similar before.

So these are the legal and illegal conditions for multiple o'clock properties. And lastly, this is rather intuitive and obvious. You're pretty different clocks, but you have an overlapping we should be illegal, or we should not work but we did advance the clock explicitly with Hong Kong one. So that should be legal. Again, this is this is all true for 2005 in 2009, and fro even if you don't have BonBon one, it is still legal as shown in this particular second example here. So folks, this is a very high level description of multiple a clock property.

And sequences. This subject can itself take quite a few hours. But I think you have a very good understanding of the basic semantics and how to read or how to design multiple clock properties. So please experiment further and use the fundamental knowledge that is presented here. And you should be able to design your multiply clock properties in sequences. Thanks a lot for attending the lecture, and I'll see you soon in the next lecture.

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