Introduction

SystemVerilog Assertions and Functional Coverage From Scratch SystemVerilog Functional Coverage Introduction and Methodology
6 minutes
Share the link to this page
Copied
  Completed
You need to have access to the item to view this lesson.
One-time Fee
$39.95
List Price:  $149.95
You save:  $110
₹1,480
List Price:  ₹9,995
You save:  ₹8,515
€36.82
List Price:  €138.22
You save:  €101.39
£31.35
List Price:  £117.69
You save:  £86.33
CA$54.61
List Price:  CA$205
You save:  CA$150.38
A$60.23
List Price:  A$226.10
You save:  A$165.86
S$53.93
List Price:  S$202.44
You save:  S$148.51
HK$311.97
List Price:  HK$1,170.98
You save:  HK$859.01
CHF 36.57
List Price:  CHF 137.29
You save:  CHF 100.71
NOK kr422.78
List Price:  NOK kr1,586.89
You save:  NOK kr1,164.11
DKK kr274.91
List Price:  DKK kr1,031.86
You save:  DKK kr756.95
NZ$65.26
List Price:  NZ$244.95
You save:  NZ$179.69
د.إ146.73
List Price:  د.إ550.76
You save:  د.إ404.03
৳4,680.55
List Price:  ৳17,568.19
You save:  ৳12,887.63
RM187.94
List Price:  RM705.43
You save:  RM517.49
₦58,378.88
List Price:  ₦219,121.76
You save:  ₦160,742.87
₨11,100.64
List Price:  ₨41,665.63
You save:  ₨30,564.99
฿1,461.83
List Price:  ฿5,486.92
You save:  ฿4,025.08
₺1,286.90
List Price:  ₺4,830.33
You save:  ₺3,543.42
B$206.42
List Price:  B$774.80
You save:  B$568.38
R735.85
List Price:  R2,761.99
You save:  R2,026.14
Лв71.98
List Price:  Лв270.20
You save:  Лв198.21
₩54,599.66
List Price:  ₩204,936.66
You save:  ₩150,337
₪146.18
List Price:  ₪548.70
You save:  ₪402.51
₱2,325.26
List Price:  ₱8,727.76
You save:  ₱6,402.49
¥6,269.95
List Price:  ¥23,533.90
You save:  ¥17,263.95
MX$667.15
List Price:  MX$2,504.13
You save:  MX$1,836.97
QR145.50
List Price:  QR546.15
You save:  QR400.64
P542.15
List Price:  P2,034.93
You save:  P1,492.78
KSh5,207.28
List Price:  KSh19,545.24
You save:  KSh14,337.95
E£1,882.63
List Price:  E£7,066.37
You save:  E£5,183.73
ብር2,292.75
List Price:  ብር8,605.70
You save:  ብር6,312.95
Kz33,891.94
List Price:  Kz127,211.43
You save:  Kz93,319.49
CLP$36,219.86
List Price:  CLP$135,949.16
You save:  CLP$99,729.30
CN¥284.06
List Price:  CN¥1,066.21
You save:  CN¥782.15
RD$2,349.84
List Price:  RD$8,820.01
You save:  RD$6,470.17
DA5,371.51
List Price:  DA20,161.67
You save:  DA14,790.16
FJ$90.59
List Price:  FJ$340.03
You save:  FJ$249.44
Q309.96
List Price:  Q1,163.43
You save:  Q853.46
GY$8,348.51
List Price:  GY$31,335.65
You save:  GY$22,987.14
ISK kr5,521.09
List Price:  ISK kr20,723.09
You save:  ISK kr15,202
DH398.02
List Price:  DH1,493.97
You save:  DH1,095.94
L707.89
List Price:  L2,657.05
You save:  L1,949.15
ден2,267.94
List Price:  ден8,512.61
You save:  ден6,244.66
MOP$321.11
List Price:  MOP$1,205.29
You save:  MOP$884.17
N$733.36
List Price:  N$2,752.65
You save:  N$2,019.28
C$1,468.65
List Price:  C$5,512.51
You save:  C$4,043.85
रु5,306.59
List Price:  रु19,917.99
You save:  रु14,611.39
S/149.17
List Price:  S/559.92
You save:  S/410.75
K155.07
List Price:  K582.06
You save:  K426.98
SAR149.80
List Price:  SAR562.28
You save:  SAR412.47
ZK1,065.01
List Price:  ZK3,997.46
You save:  ZK2,932.45
L183.21
List Price:  L687.70
You save:  L504.48
Kč907.36
List Price:  Kč3,405.72
You save:  Kč2,498.36
Ft14,132.58
List Price:  Ft53,045.85
You save:  Ft38,913.26
SEK kr426.20
List Price:  SEK kr1,599.72
You save:  SEK kr1,173.52
ARS$35,575.87
List Price:  ARS$133,531.97
You save:  ARS$97,956.09
Bs275.73
List Price:  Bs1,034.94
You save:  Bs759.21
COP$154,396.52
List Price:  COP$579,518.37
You save:  COP$425,121.85
₡20,458.11
List Price:  ₡76,788.33
You save:  ₡56,330.22
L986.09
List Price:  L3,701.25
You save:  L2,715.16
₲300,135.95
List Price:  ₲1,126,542.82
You save:  ₲826,406.87
$U1,535.64
List Price:  $U5,763.95
You save:  $U4,228.31
zł156.61
List Price:  zł587.85
You save:  zł431.23
Subscription
$149.95
$39.95
per week
Payment Plan
$149.96
$39.95
per week
4 payments
Already have an account? Log In

Transcript

Hello and welcome to the course on system Verilog functional coverage. This is a comprehensive course which will guide you step by step through the language, methodology and applications. The main goal of this course is to help you achieve an objective measure of the functional coverage of your design and test match. This course has nine lectures. This is simply a copyright notice, telling you that the course has been copyrighted. A bit about myself.

My name is Ashok Mehta. I've been a CPU and SOC design and verification engineer for over 30 years. I have 13 patents issued on SOC and 3d ic design verification. And I also published a book on system Verilog assertions and functional coverage in 2014. It was published by Springer. So let's see how did this course help you?

The foremost gain from this course is that you will objectively be able to measure the functional coverage of your test image and design. There is no subjectivity here the language will help you make sure that you are functionally covered everything in your design. And in today's design verification landscape, this is a very important part of overall functional verification methodology. And I believe that all the verification engineers do need this knowledge to be successful. And it will also be a highlight of your resume, as most of the employers now require you to know function coverage fundamentals. This course as I said earlier, will not only provide you a step by step guide to the learning or the language, but also it will show you your real life applications to solidify your concepts.

Okay, let's first see how functional coverage fits under the overall IEEE 1800 standard system or log language, even though most people think that system Verilog is just but one language, there are indeed sub languages under this umbrella. So let's start with your duty your design under test, you need to provide the simulators, you need to check the response. And now even increasingly important, you have to know if you have covered everything in your design. In other words, you can also say, easier test bench comprehensive. If the test bench is not comprehensive, then your coverage will not be comprehensive. So in some sense, it's a measure of your test page also.

Now, under the system Verilog language, you have a complete set of features, which are like classes are also known as object oriented programming features. It is under this feature set that the universal verification methodology fits And also you have constrained random features. So those are what I call test which controls the other sub language as I call it is functional coverage language. We discover groups and cover points that we will soon see in other language. Know that the functional coverage language is orthogonal, meaning its syntax and semantics is different from the OP syntax and semantics constrained random syntax and also orthogonal to the system, such as language. In other words for you to learn functional coverage language, under system Verilog, you don't really need to know or P or the SBA.

Okay, the important thing that we need to understand during this introductory lecture is the difference between code coverage and functional coverage. code coverage, as you probably know is derived from directly from the design, it is not user specified. You simply give your RTL design to a given simulator, turn on the code coverage and you get the code coverage of things like branch expressions, state transitions, case statements, etc. In other words, that design structure has been covered not the intent. So, it does not evaluate the intent of the design, what is it that the design really wants to do? For example, let's say your end of specifying bus grant equal to bus request and idle or bank reset.

This is what you write in your RTL code. code coverage will go through and tell you if reset have been exercised idle have an exercise bus request has been exercised and thereby bus Grant has been exercised. He does not know whether this equation is correct or not. So if you Your intent was at bus grinding call the bus requests and idle and bank reset code coverage has no idea. That's our functional coverage comes into picture. So functional coverage is user specified.

You tell the simulator, this is the function this is the intent I want to cover. So, obviously is based on design spec, you read the design spec and you decide what is it that you want to cover functionally. So, it will give you an answer in an objective manner rather than guessing. Hey, can we tape out? This is probably the most important question you face during any SOC project. And just a couple of points on what kind of functional coverage for example control oriented coverage, have I exercise all possible protocols that the recycled supports, burst, non burst etc.

And there is also what I called Data oriented coverage, how are exercised the cache line at all granular levels, byte word, quad, quad word, etc. So this kind of control coverage and data oriented coverage is simply not possible with code coverage. And that's what functional coverage really comes into picture and you will see a lot more different types of control and data oriented coverage in coming lectures. So that's all folks for this introductory lecture. Thanks for attending. And I will soon see you in the next lecture.

Sign Up

Share

Share with friends, get 20% off
Invite your friends to LearnDesk learning marketplace. For each purchase they make, you get 20% off (upto $10) on your next purchase.