Sampled Value Functions (Part 1): $rose, $fell

SystemVerilog Assertions and Functional Coverage From Scratch Concurrent Assertions – Sampled Value Function
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Hello, and welcome to lecture number eight. In this lecture, we will examine and study what is known as sample value functions. And I will explain to you, of course, why they are called sample value functions. So let's start with two of the sample value functions. One is dollar rows, dollar rows, here's the syntax, dollar rows have an expression, and you can have an explicit clocking event. Or you don't need it.

It's, it's, it's an optional thing. And I will show you when you really need it. The important thing to understand here is that it will return true if the least significant bit of the expression change to one from the previous take of the talking event. So let's say if you have a bus of 32 bits, and you said dollar rose, it won't look for the entire 32 big buzz to go from From zero to one, it will only look at the least significant bit of that buzz. And if that significant bit goes from zero to one, then dollar roses will be considered to be true. Also note that, just like in Verilog, it's it's a transition could be zero to one x to one or zero to one, anything that goes to one or that rises to one.

But now I want to point out a very important difference. dollar Rose is not dollar balls edge is a big difference. Balls edge means anytime, anytime a signal goes from zero to one, it's a positive in very low cost system or low. dollar rose on the other hand is at this clock. Any clock at a given clock if the sample value or The expression in the pre pond region is one. And if the sample value of the expression in the previous Clarke's pre pond region was zero, or x or z, then it dollar rose will be considered to pass.

So it's between two clocks. And it's not an immediate project kind of semantic is between two clocks. And between these two clocks, one clock now and one clock in the past the sample value of the expression in the pre pond region. If you're not familiar, or you did not get the concept, please go back to the lecture where I talk about frequent region. And because it's a sample value between two clocks, that gets evaluated and then you determine whether dollar rolls occurred or not, is why they are called sample value functions. Similar to dollar rows there is Dollar fell identical, only that the least significant bit should be zero from the previous state of the grokking event again, the current sample value in the proposed region is zero, the sample value in the prepon region of the previous clock was one or X or Z, then Dollar fell is considered to pass.

So, the the other point I want to point out and some people miss this, let's say at the very first clock, this is your very first clock day, you don't really have the previous clock, then obviously the value is compared against x. And this is something that you need to know because many times during initial time, assertions fire they fail, they don't fail and is easy to miss that everything is compared against x because There is no previous talk. And and the as I just said the clocking event is optional. And it's usually derived from the clocking event of the assertion either the assertion like we have seen or from the input clock of the procedural block. And I will show you in in in just the next couple of slides what that means. So, this functions can be used in properties of sequences, as well as procedural code and I'll show you an example of all three on how they can be used.

Okay, let's see dollar rose. So here I'm saying property check, I act at pauses of clock, you need an edge in any concurrent assertions. So I pause of talk, which is a sampling edge, dollar rose interrupt, non overlapping implies dollar rows. Many if at this clock you see dollar rows interrupt interrupt has gone to one in the pre porn region and was zero in the previous clock prepon region then at the next clock I should go Hi. So, here is the timing diagram and you can see that at this clock edge interrupt goes interrupt does not go higher this clock edge in the pre pawn region it was one which is here before clock went high in the prepon region right here right now Delta before the clock edge and it goes zero in the pre planned region of the previous clock tick and said this this clock edge is considered dollar rose.

Same theory applies. So, at this clock a it's considered dollar rose I egg or rise I And then the property passes. But if dollar rose interrupt takes place at this college of clock, and is indeed one at this quality of clock, it's a level sensitive one, what we expected was that it should rise from the previous clock, it doesn't end the property phase. Now, why is edge detection useful? Why Why is it useful? Why can't I just use level sensitive?

So let's say you use level sensitive in in this example we did a sensitive interrupt at sensitive I. In this example I'm doing level sensitive interrupt implies that I will be true the next clock. Okay. So this was going to happen, let's say DeRose and dollar rose here and dollars. Rose is here at the clock edge, it goes up on here in the prepon region, it was a one here it was a one here in the pre pond region and this property will pass because the level was one it before the interrupt Anya is at two clocks and as required by the property will pass. But So will this there is an edge here, but at level level was one and at the next clock level was one and the property will pass you if you are expecting an edge on an ayah that you have made a mistaken identity assertion.

But more importantly, and this is an it's a very important point that you need to remember when you design your assertions. See what's happening here is we have a level sensitive interrupt and level sensitive. I remember when I say level sensitive is the antecedent. That's levels in To do and if the consequences level sensitive, not the sampling edge, sampling edge will always be edge sensitive. Okay, so interrupt, as you can see in this diagram, for example, entropy is one at this clock is one, it's one, and it says one, every clause that it will sample interrupt will be one, it will keep firing this property, again and again and again. So if you're simply trying to say that whenever there is interrupt that I actually come the next clock and then you're done.

That's not that's not what's going to happen with this particular property. So I strongly recommend that your antecedent should be as sensitive to the extent possible, there will be times when you cannot have an as sensitive and just hit it, and that's fine. But in this case, if you were expecting this behavior, The left hand side of the timing diagram here, then this assertion will simply consume your simulation time for no reason. And you will get false positive. So So let's say you go ahead and say okay, I'll go ahead and do an edge sensitive on the consequent. But remember interrupt is still level sensitive.

So what's going to happen? This will pass because dollar Rose is at this pause, it is true. And intervals one doesn't matter whether it went to one or it was one at this sampling edge in the prepon region and this will pass but guess what? Since this is level sensitive, the next clock right here, interrupt a sample highs so the property is going to fire again and that is going to look for door rolls is Well guess what, once the IQ is high, it's just going to remain high. And this will fake. So if you're designing this way, and if there's a failure, you will be totally confused as to why is it failing?

It did pass. I did get my iron for the intro, but now why is it failing? So the bottom line is you, you basically have to have in this particular case, and I'm just showing you the Dollar fell and as sensitive behavior on both the antecedent and consequent, so Dollar fell request, and I'm saying es fel grad, as well as a sequence I'm just making it a bit more interesting. And inside there is a formula called a which gets the actual grind and everything dollar for dollar fell grant. And he has a very simple application, but I'm showing you Simple applications, but these applications are very useful. So, and you will see that some of the simpler assertions will give you more bang for your buck.

So, here I'm saying whenever right enable is asserted, that means it goes lower is an active low signal that at the same time because this is an overlapping implication, that right data cannot be a No, we haven't seen a reason not but you can logically intuitively figure out what that means. Now, as I was telling you earlier, dollar rows and Dollar fell can be used in sequence property or procedural block also. Now here, let's say in this procedural block, were saying always at positive clock, cordon is equal to send cnn And dollar rose ice cream down. This is amazingly powerful, you have a level sensitive that is done bitwise AND with an X sensitive or sampled quote unquote value function can be combined in a in a Boolean. Now you can see that dollar rose I assumed and does not have a clock. So, the clock is infer from the always block, which is the part of the dollar rose or Dollar fell definition.

More interestingly, for example, I want to assert system exception, if two interrupts go higher at the same time it's unknown and the entire system is going to fall apart. You can do that you This is impossible in Verilog. You cannot have two edge sensitive constructs anded together So you can do this and again for both of dollar rows, the clock is inferred from the previous or the always at pause, positive clock. You can use dollar rows and dollar fail even in continuous assignment. These are very powerful continuous assignment, you can use them. Procedural block, you can use them sequences, you can use them properties, you can use them.

And here the key thing you need to note is that it's a continuous assignment. There is no inference of cloud from a procedural blog. There is no inference of cloud from sequence or property. So you have to explicitly provide the sampling edge within the continuous assignment. So that's the key unit to remember if you use that in the continuous assignment.

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