Performance Implications and Coverage Methodology

SystemVerilog Assertions and Functional Coverage From Scratch Performance Implications and Coverage Methodology
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Transcript

Hello and welcome to lecture number eight. In this lecture let us discuss a bit on performance implications of when bought and how you should cover. So, the first question is what you should cover you need to be very careful on how you create a PowerPoint and the bids. For example, let's say you have a 32 bit address bus like we, I've mostly shown you for bid address versus in the previous lectures, but more than likely will have a 32 bit address as well. You do not want to cover many cover meaning your test match does not need to create to raise to 32 different addresses to make sure that the address process covered because it's a good chance that if address zero is covered, it is one is covered. But what is important is for example, the by word the word aligned addresses are covered starting And addresses are covered, page crossing addresses are covered.

Those are the things that your test page needs to exercise. But if you try to cover the entire 32 bit address was first of all, you will not have enough simulation time for sure your test bench will be totally redundant and absolutely waste of time all over. So just be absolutely careful on you understand what you should cover. For example, another example is let's say you have a counter, there is no need to go to the entire count or the counter range. What is important is for example, only the roll over counter values. Whenever the counter goes from all ones or zeros, you may have a bug or the counter may not act accordingly and that's what you want to cover.

That's what you want to make sure that your test bench exercises. Another example let's say you have to KD FIFO you're not going to Right to each of the entry of the took a five four and read from each of the entry of the two care FIFO to make sure that the FIFO works, you will randomly write and read from a few locations and if that work then was important to cover for example, for something like a FIFO is you want to make sure that you have exercise your test might have driven condition such that five four does become full. And then see what how the design reacts when the five four is full. For example, when you try to write to a five for that is full what happens or greater conditions said that the fiber is empty. Okay, and here 544 for example, cross with five foot push, like I just said, you know, you cross the two that means you have to make sure that your test bench not only drove conditions to make the FIFO full, but when the FIFO was full, it also tried to push another item To the FIFO.

Now, that's where you may have a bug and similarly cross five four empty with FIFO read and this is where the the cross coverage comes into picture that we saw in the previous lectures. So, not only what you should cover is important, you also need to understand when you should cover So, for example, let's say you want to disable the coverage during reset simple as simple can get there is no point in trying to cover things during reset. All these have performance implications. The second thing is for example, you have a test mode signal. Now, try to cover the test mode signal only when you are in test mode, which is basically in j tech tap controller. If the TMA signal is asserted, then only the remaining boundary scan in our SMS signals have us or are important.

So cover only when the TMS is asserted. And then I will show you in the next slide also you can make effective use of coverage methods such as START STOP sample started this particular condition stop at this particular condition and sample in between, as I will show you the very next slide. So, overall unit to be very careful because if you end up creating hundreds of thousands of bins and PowerPoints, too many issues with that one is your coverage report will be so huge. You would not know what you're looking for. And the second thing is your simulation will drag if you're trying to cover so many things. And again, it is at this point knowing what you should cover is where the illegal means.

Ignore beans, cross beans, transition Beans, beans have interesting All these features that we discuss come into picture because that's how you narrow down or pare down the number of bins and the car points. And one more point, which is we haven't covered symbolic assertions in this course, because that's outside the scope of the course. But like I said in the very first lecture, so several other sessions have a keyword called cover and that cover will help you cover very low level temporal domain conditions. That means Have you exercise this temporal domain condition. So all those temporal domain conditions transitions that you cover with the SVR cover, you do not want to repeat those and put those into the cover group score points and for example, transition cover, think of transition cover in the functional coverage more as a transaction level transition coverage. While the transitions that take place in the system where log assertions were removed, At signal level, this is just but one differentiation you can keep in mind.

So here's an example of when you can have, you can start stop and sample, a particular color group, for example. So here I have a core group call RG. It has two core points, and I've instantiated RG and the instance name is Maya underscore RG. And what I'm saying is always a positive request. Start sampling or start covering start collecting information for this cover group. At the borders of grind, stop gathering this particular information stop collecting the coverage information.

And anytime in between in between started strong at every positive clock. That's my sampling is I go ahead and sample the color group RG and tell me whether I've exercised the core points. note one thing here that in all the previous lectures, we covered group RG, I always showed you at pauses of clock, for example, or some sampling edge. Here, there is no sampling edge. If you as I said in the very first lecture, if you have a gold cover group without a sampling edge, then you have to explicitly sample it from a procedural block. And that's what I'm showing here.

Since there is no sampling edge, I'm going to tell it that always add pauses of claw sample, do the evaluation of this code points, so to say, but do that only between the start and stop and points. So that's all folks are very simple lecture. Very straightforward, but very important for you to keep in mind when you design your coverage. Apply. Thank you for attending and I'll see you in the next lecture.

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