'bins'

SystemVerilog Assertions and Functional Coverage From Scratch SystemVerilog Functional Coverage Language Features
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Transcript

Welcome to lecture number four. This is where we will cover the bins that I've been referring to in previous lectures. So, I will go through the basics of the bins. So to start with what is a bin, think of a bin as a bucket, in the sense that let's say for example, in this particular example, you have a DR address is of a bit wide, that means it has 256 different values that you need to cover. Now, if you just let the simulator create the bends, so called bins or buckets, it will create 256 of those, which is what you really don't need. So bins is something where you can bucket eyes or you can say hey, if the values are from zero to 10 in a day get covered, put that in this bin with this name on it and I will show you in a example which will which is example I'm carrying forward from previous lecture on PCI how it becomes useful.

So, let me not go ahead of myself. So our goal point will include a set of explicit, like I showed you in some examples before or implicit bends that will allow you to organize the cover point sample. And we haven't seen transition or transition values or cross values for that matter. So let's look at this example. I have an eight bit wide address and I created a cover group called Jeevan. And I want to sample the core group it pauses of clock, so it pauses a clock all these discover point in all these bits will be evaluated.

Now inside discover group I'm going to cover with the PowerPoint, this ADR and I evaluated only a preset is low if we are not in the reset mode. Now if you recall those To squiggly brackets. Now in the earlier example, I had nothing inside the squiggly brackets and everything was automatically generated for you. What I'm doing now is I'm going to define a bunch of bins. And since as I said, ADR has 256 different values, I'm going to show you how to put those 256 values in different bins. So let's look at the first bit.

Bins is a key word. And I'll give it a name, address bin one equal to in the squiggly bracket, zero colon three. What this number one, do not confuse zero colon three to mean that is a four bit register or anything like that, which is what you're used to. In the functional language, syntax and semantics. Zero colon three means four values. 012 and three.

So, what this is saying is that whenever address this government address has a value either zero or one or two or three, if you reach any of these four values, then you have covered address being bought. Again, do not confuse this with the register zero colon three, it literally means 012 and three and whenever it's a single big single been here and you I will show you how can you create multiple bands, but this is a single Ben took our all as well as 012 and three, anytime you reach any of these values, this bins address min one will be covered. In the second line, you'll see that these address mean two I put this bracket here and then I'm saying values four and five. What this means is that Individual beans will be created automatically generated by system our live audio simulator for that record I'm not telling it anything, it's it sees that there are two values on the right hand side so it's going to automatically create two bins.

So as you can see our individual bins address been to one these are the names given by the simulator and address been to two for each of the added value for call caller comma five. Again to contrast this with the previous line here there is a single bin to cover all the address values. Here there are two bins to cover two different values. So there is a big difference here. When address equal to four has been reached, then address been to one will be covered. And when address value five has been raised at has been to two will be covered.

Now in this line, I'm explicitly saying create two bits But I have three values six, seven and eight on the right hand side. So, what is going to do is add this value six isn't been addressed when three one and address bin two there are only two bins and three values seven and eight will be put in the second bin. What that means is, if six had been reached, if we if your test bench exercises ADR equal to six, then the then the address been three one will be considered covered and whenever the ATR it is either value seven or eight address when three two will be covered this names are given explicitly by the the simulator. This is slightly reverse of the previous line here I'm saying create three bins, but I have only two values. So, the first bin will cover very Nine second bean will cover value 10 and the third one will simply remain empty it the simulator will tell you that it's an empty bed meaning it'll never be covered.

There's nothing to cover there. Similarly, if you look at this particular line, you will see that in the address mean five again, I'm doing what I did with it trust me do. I'm basically saying create explicitly number of beans required based on the values that I want to cover on the right hand side. But what I've got on the right hand side is I have two different brackets one is took our values 910 1112 and the second is to go over 1112 1314 1516. The point I'm making here is that you have 11 and 12 and 11 and 12. In both these brackets are all overlapping and that's perfectly okay.

That's perfectly okay. What the simulator will do is it will remove the riddle Then see and basically go from nine to 16. And because I'm saying similar, you create the bins. Here, we'll create eight bins explicitly for the eight values on the right hand side. And here, we are saying that cover all the values of the ADR that are between 31. And Forever Forever means in this case is 256.

So any address value, you read that as value anywhere from 31 to 256, it's considered covered. And these bins here Greg will tell you that those values have been covered. Any of those value covered will be considered. We'll consider this beans here too, and to be covered. There, it's important to note and here I have covered all the values but in case you did not cover all the values, then you can just put a default here. So anything That's not been covered in the previous bins.

But all of those anything that you reach by I consider that as a default and put that in the bins, others. So these are the different ways you can create vents and again, a Benyus value bucket guys, you basically say, Hey, listen, I have a 32 bit wide bus. And I don't want I want less than the first eight bits to be. If they get covered, put them in this bin, so it's easier for me to see my coverage report and so on and so forth. Now, let me show you an example. Which will solidify this concept.

So this is the same example I showed you in the previous lecture. There is an enum which is 12 different cycle types of the PCI bus and the enum is called PCI commands. I have created a power group RPC commands under scope cover just like in the previous lecture, and I'm sampling it at the age of four. Now, earlier I simply said cover point PCA commands. And then I left it up to the similar to create 12 bins for the 12 nm types add for further total enum values. Here, what I'm doing is I'm going to create a bins are being called PCI reads.

And what I'm telling the simulator is create all the bases necessary to cover all the right hand side values. And in the PCI rates, I want to cover all the read type cycles that the PCI come at the PCI bus issues in the PCI writes when I want to cover all the memory, sorry, all the right commands, and whatever that is left I want to put that in the beans called PCM miscellaneous misc. So as you can see beans Live you now when you look at the coverage reports, and if you see beans PCI reads have been covered, then you know that all the read cycles have been covered. If you did not classify them into READ WRITE and miscellaneous, for example, then you have to look at individual beans of all the 12 beans that are explicitly created for you and see a harmony. If all the reads have been covered.

This makes it a lot easier. And so this is one of the main reasons for creating veins. And you will see how it affects even further when we go to the transition and cross coverage. So that's all folks. I just wanted to introduce you to Ben's, how to create ways what are the different type of vents and again, being is simply a way to organize all the different values of the PowerPoint that you're trying to cover. Thank you very much for your time and I will see you in the next class.

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