QUIZ 4: PCI Bus Protocol

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Hello and welcome to the quiz on PCI rate protocol. In this quiz, I'll present a simple PCI master and target system. And in the lab will of course, learn about temporal domain assertions at sensitive assemble value functions, consecutive reputation, Boolean expressions, etc. So here's a very simple PCI system. So to say, PCI is a parallel bus compared to the latest PCI Express, which is a serial bus. So in this system, you will have a PCI master a PCI target and PCI protocol property This is where you will code your properties.

And under the test, we say protocol module all three are associated. So in system, the master drives or frame indicating the start of a cycle then if a service is ready meaning the initiator or master is ready, then it drives commands and vital levels while the target decodes the address put on the bus and assess device select if it has been selected, and then it says t ready to indicate that it is ready to receive or transmit data and then address and data bus which are obviously bi directional and then you have your reset and clock. Here's a simple PCI read protocol. PCI bus is a very complex bus and I have only chosen the right protocol for this spreads. So as I was saying, the transactions starts when frame is asserted low and when frame is asserted that PCI master will address and byte intervals on the bus, meaning they are qualified when crime is asserted low.

And then it would want to start transferring data, while target decodes the address that is put on the bus and considers itself selected if that was belongs to the target. And then once a Master says that I'm ready, that target may or may not be ready. So the next word target is not ready yet we are in great state. But the clock after that target said I'm ready. So at that time I ready is assert 811 is asserted and device elect is asserted and the data transfer takes place. Then target says I'm not ready for the next data transfer.

So it goes into a wait state and so on and so forth. So this is how data transfer takes place in a in a PCI system. So there are Five different checks that you need to call and these are very simple assertions and what are the things I like to say that when you look at this bus protocol, you can think of some other checks also that you would like to code. So, you can go beyond this five checks. So, the first check is that on falling at your frame address, a data bidirectional bus and command and vital revolvers cannot be unknown. So, sometimes, this simple assertion will catch many errors.

And then when both Iranian t radio are asserted, that ad again a dn CBE cannot be unknown. And then when frame can be D asserted only if it is asserted. So here, you look at the the frame the frame meaning the bus is over is is asserted going high only when I ready is still low. So, at this clock frame can be asserted only if I read is low and then I read he will complete the very next crop. So, we need to check for that ad t ready can be asserted only if device selected asserted so. So, here for example, this T ready cannot be asserted, if device select is not asserted.

So, T ready can be asserted only if device selected asserted. And finally, once the cycle starts that is the frame is asserted, command and byte interval bus cannot flow and it should remain in non flow condition until frame is d Ascetic. So, these are the five checks that we would like to code in this quiz. So let me show you a bit about the and all the files that you need are available on my website, which is defined here.com slash BNF. The lab files. This is the page where all the labs have input, meaning all the files that you can download.

So for this particular quiz, look for a Udemy lab PC protocol, and you will see all the files, the master target files as well as all the compile and run scripts that are on the page, simply download them and simulate them. So let me show you a few of the files, PCI master dot v. You really don't need to understand this file. This is just to show that there is a PCI master dot v module is a simple state machine. Customized basically to do a read transaction Then there is the PCI target.me which is which is reflective of the target module and again another simple state machine that completes basically a read cycle. And when you look at this code you may get a little outrageous, should I say confused because I have lots of if def and these if tariffs are there to introduce specific bugs into the design so that the assertion that your code can catch this bugs, then, then the next file is of interest to you.

So, here's the fine ready we'll call your assertions is called PCI protocol property dot v. So, it is fine just like in all the other quizzes, I have put in a dummy line meaning you are To delete this line and put the correct assertion that you need, everything else is given there for you, including the sampling edge, and assertion of property and everything, all you have to do is delete this line and put your particular assertion in there. And so that's true for Jacquard check to check three check for and check fi everywhere, simply delete this slide and put your code in there. And then there is the test, test PCI protocol module where I'm instantiating master target and the property module. And we are all connected via the airports. And then all I do is simply do a reset of the system. So let's see how how you would run this particular lab.

So, graded directory, whatever you want to call it. And then open PCI protocol property.sv that I just showed you this why and and remove the dummy line and put your code in there. And then after removing the dummy line and coding your assertion, you will you will do this for basically all the checks check 1234 and five now every time you change and add your assertion for example for check one, then run run underscore check one.do. Now this commands let me show you the file run check one dot two. Now this file is created all the commands are that for Cuesta mentors quest simulator, so if you had to use it cadence, incisive or synopsis vcas you will have to change the compile and simulation commands, but request Are you compiled with V log, and then you simulate with the VC. So you don't need to worry about how this file works.

All you do is inside the question simulator said do a run underscore check one.do and it will simulate and create the log file. The log file will be created a test PCI protocol check one dot log. Similarly, for check two, there's a do file check three, four and five there are do fives and each simulation will create either check one dot log check two dot log, and so on and so forth. So basically, this is how you simulate chain the PCI protocol property.sv for a given check, and then do run check one.do or for the other checks the same way. Now So that is how you can very simple all everything you need has been given to you. And now let's look at the solution.

So as I've said in my previous squeezes, even though I'm giving you the solution, at least tie my solution into the PCA protocol dot v phi by removing the Gumby line and at least code exactly what I have. I have shown here and again, rerun the run check one or two or the other.do files. So that way you can see in the submission log file that the the check and the assertion have fired and the bug have been detected. So the first check is on falling edge of frame address and command by Carnaval cannot be unknown. So it's a very simple assertion. All you have to do is add pauses of clock everything is based on the sampling as positive of a desirable if and only if reset.

And, like in every assertion that I've taught you during the course always try to figure out what the antecedent is. So, in this case everything seems to start for this particular check, but frame is asserted, meaning it goes from high to low. So whenever frame is a certain starting that clock overlapping operator, ad cannot be unknown, or CMV cannot be unknown. So that's it in a simple Boolean. With function, you can check to see whether address and command lines are not unknown. Now Believe me this is a very simple assertion, but when you start tackling your project rights are similar assertions and you'll be surprised how many bugs you'll find just with a simple assertion that jak two is when I read E and D ready or assert a that address and command cannot be in unknown state.

So, here the antecedent is that at bothers of law, if I ready is low and T ready is low, that address and command and vital level cannot be in a known state. So that's quoted this way. So here the antecedent is different from the check one antecedent, and the third is when frame frame can go higher only if I already is asserted. So again, the antecedent here is that if frame goes from zero to one, it means that at that time overlapping already is low. So if at all the frame goes high, and I ready Not low, either in the weight phase or data transfer phase, then it's about and again a simple assertion like this will check for the precept protocol very nicely. And similarly, check number four, where t ready can be asserted only if device electors asserted.

Now, this looks very benign. So, let me show you how you can make a mistake. So, T ready can be assert a bank t ready eight means that at that time device elect is also low. But in case you end up coding saying that if device elect is low than T ready is low thinking that is one in the same this is incorrect. Why? Because, if you you have to carefully look at the specification.

If device elect is low, then t ready may or may not be low and is not required. device can be selected but target may not be ready. So this if you just reverse these two signals, you are coding an incorrect assertion. When t ready is low, device select must be low, but when device select is low, it's not necessary the tea ready must be low. So read the specification very carefully, otherwise you will make mistakes in your own assertion. And check that once the cycle starts which is when the frame is asserted.

Command align should not flow until frame is yesterday. So we don't know when the frame is gonna be the asset and the cycle can be hundreds of clocks long. So the way to do this is again what is the antecedent antecedent is the assertion of frame so when Dollar fell frame and frame goes high to low commodity byte enable bugs cannot be unknown with a bang here until many this behavior should continue from now until forever until frame is the asserted meaning it goes from low to high. So, we have seen consecutive reputation operators in many examples and is one of the most powerful features of the language. So, again command right enable cannot be a node and this behavior this particular behavior should continue consecutively it should remain not unknown, until the way to read this is until frame is deserted. Now, in 2012 LRM there is an operator called until go make life even easier.

So, one of my suggestion would be To remove this particular line, this particular operator consecutive reputation operator and use until instead of these words here, put until and see how it works. So, again, these are very simple assertions. But just like with other quizzes, see if you can find more specifications for which you need to write assertions, and also try to write the same assertion with different operators. There is no one way to write an assertion. So that's pretty much it. It's a simple quiz.

All the files you need are available on my website. All the four quiz files are available on the website and for PCI protocols, they are here. Thank you.

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