Chapter Five counters and shift registers. If we examine a four bit binary count sequence from 0000 to 1111, a definite pattern will be evident in the oscillations of the bits between zero and one. Let me describe that a little bit further Note how the least significant bit toggles between zero and one for every step in the count sequence. While each succeeding bit toggles at one half the frequency of the one before the most significant bits only toggles once during the entire 16 step count sequence of transitions between 700 sorry, seven which is 01. One, one, and eight, which is 1000. If we wanted to design a digital circuit to count in four bit binary, all we'd have to do is design a series of frequency divider circuits.

Each circuit dividing the frequency of the square wave pulse by a factor of two. JK flip flops are ideally suited for this task, because they have the ability to toggle their input states at the command of a clock pulse. When both J and K inputs are made high or a one. Let's have a look at that. So here we have a JK flip flop that is connected such that the J and the K are being held in the one logic position by the power supply DDD. If you would And hence the clock pulse coming in, which we call signal a is going to be clocking the JK flip flop to exactly flip flop every time that there is a positive going signal coming into the clock pulse.

If we consider the two signals, one coming into the clock input being signal a and then we measure signal be coming out the other side. It would look like this over a period of time. And it represents basically a two bit binary number signal a being the least significant bit and signal B being the most significant bit. We see that the count sequence however is backwards as you start to go from left to right, you'll see the bits will be changing from one one to one zero to 01 and back to 00 again Although this may not be counting in the right direction, it is as least it is counting and it could be considered a counter. This is how I JK flip flops can be used for counting. However, we would like it to count in a positive direction and we're going to have a look at that in the next.

So now we're going to look at a four bit up counter. And in this case you have four JK flip flops that are being held the inputs are being held to JK inputs are being held at logic one level so they will act as a toggling device. That is when the clock pulse hits the C input whether it's positive going or negative going depending on what it's looking for. It will toggle each one of the The JK flip flops to the next position or the inverse position. If we used flip flops with negative edge triggering, and the bubbles are indicating that on the input, and we're only using the last three JK flip flops as negative triggered JK flip flops, we could connect the clock input of each flip flop to the Q output of the flip flop before it so that when a bit before it changes from a one to zero, the falling edge of that signal would clock the next flip flop to toggle to the next bit.

This circuit would yield the following output waveforms when the when clocked by a repetitive source of pulses from an oscillator the first flip flop the watch With the q naught output has a positive edge triggering clock input. So it toggles with each rising edge of the clock signal as indicated by the other arrows. In the pulse diagram each succeeding output bit is toggled by the action of the preceding bit, transitioning from high to low. This is the pattern necessary to generate an up count sequence. The D flip flop is our simplest form of serial in serial out shift register, it is a single bit shift register, and the data coming in on D can be shifted to Q. When the clock pulse goes from zero to one.

It's a positive going triggers flip flop. So in its simplistic form, this is a shift register the all the data that's coming in on D, whether it's synchronized, the clock or not, will be shifted over to Q on the next positive going signal that the clock puts into it. If the clock is stopped, in other words, it doesn't have any more triggering, the data that last came through will be stored at the queue position. This is in its simplest form, a single bit serial in serial out shift register. If we cascade these units together, which we will look at in a minute, they will hold more than one bit of data shifting down the system. Here we have a little bit more sophisticated shift register.

It is a might be considered a three bit shift register. And it's just three d flip flops that are cascaded together, the output of one q output of one is input to the D input of the next one down the line and the Q output of that one is put into the D input of the next one down the line. As the data starts to come in from the first flip flop D, def clock pulse going from positive to negative, we'll shift that the data from D to QA. This the data that's on cue, cue a bit before the pulse that's on D will be shifted to QB. And the data that's on the D for QC will be shifted to QC on that clock pulse. So if you consider a series of ones and zeros being on the D input sore the queue outputs that in that data will be shifted from left to right turn from left to right with each positive going clock pulse, and that will happen continually as long as the clock is pulsing, you can control that shift and there are several ways of doing it and there are sophisticated ways of doing it, but the here is a simplistic way is a simple end gate and the clock can be coming in to the end gate and you can have it enable coming into that end gate so that the data will not be shifted unless the Enable pulse or the Enable is at a one level.

Once that enable input to the end gate goes one then all the clock pulses will go through to the clock inputs to the shift registers and all the data from the D will be shown through to the queues so that the data we say is shifted serially down the line. Here we have a three bit shift register made up this type of JK flip flops. They are cascaded together. In other words, the Q output of one is the J input of the subsequent one down the line and the not q output of one is connected to the K input of the next shift register down the line. And you can cascade as many of these as you want together. We're only going to look at three bits just to get a feel for it.

But you could keep on cascading multiple flip flops down the line is depending on how many how big a bit register that you want to use the data coming in. To the JK flip flop is controlled in such a manner that it is, is connected directly to the first j input. But the data goes through an inverter before it's connected to the first k input. that assures that the J and the K are inverse of each other so that when a clock pulse and as a negative clock pulse, this time it will trigger the JK flip flop will indeed, transverse the data from the JK to the Q and the Q not subsequently, for each JK flip flop down the line. So we have data coming in at the top to the J input and subsequently inverted through to the K input. Every time the clock pulse goes negative.

The data from the left hand side of the flip flop JK will be transferred to the right hand side and the data of each subsequent JK Flip Flop will do that every time the clock pulse goes negative. So this indeed is another form of a serial in serial out shift register, because the data coming in gets shifted down the line and you can control and stop the flow of that data. And once you stop the flow of it, the data will remain on the Q output stages until it's needed to be transferred serially down the line. And you can do that the same way as we did with a with a D flip flop before by putting an end gate on the clock impulse and and putting an enable pulse, which will enable the flow of data to go from left to right. Of course, timing and synchronization is important and peripheral circuits have to be built around this shift register.

But this is an essence of one of the configurations that could be used to bring serial data out in a parallel fashion and this ends chapter five